Resources and Status
FP functional units
Most of the variable in the simulation process on ReCSiP are expressed as single-precision floating-point numbers. The format of FP numbers in ReCSiP is based on IEEE-754, but a special format in 35bits (1 sign + 23 fraction + 8 exponent + 1 guard + 1 round + 1 sticky) to minimize effect of rounding errors. The embedded memory blocks on Xilinx's FPGA are suitable to keep this 35-bit width variable, since they have 36-bit width (32 for data + 4 for parity.)
- Single-precision FP units
- Adder/subtracter (7-stages pipelined)
- Multiplier (9-stages pipelined)
- Divider (18-stages pipelined)
- Unpack/repack units
- Unpack (32bit IEEE format -> 35bit ReCSiP format)
- Repack (35bit ReCSiP format -> 32bit IEEE format)
These modules will be soon available under LGPL license.
The Solver Core Library
Solver cores are the heart of ReCSiP, which are the HDL implementation of rate-law functions. Solver cores can be connected with desired integration modules to run simulations. Currently, 19 rate-law functions in the 33 functions defined in SBML Level1.
The list and specification of the core library will be soon appeared on this website.
Integration Modules
Integration modules are numerical integrators written in HDL, which has the capability to process simple reaction pathways. An integration module has some memory blocks, to keep the reaction pathway, concentration of reactants, and simulation parameters.
A "solver" consists of an integration module and a solver can process a small reaction pathway that contains only the reactions that are supported by the solver core. When a large pathway containing multiple types of reaction mechanisms is given, some different solvers are required to run the simulations.
Currently, the integration module with Euler's method is available. RK4 and Heun will be available in 2Q05.
- 1st-order Euler (working)
- 4th-order Runge-Kutta
Software
Software components are now under development. The basic algorithm of Scheduler and its implementation is already done in 2004.
- Frameworks
- SCML: Solver Configuration Markup Language
- Software Components
- Optimizer
- Scheduler
Boards
ReCSiP Board
ReCSiP Board is our first 64bit/66MHz PCI card, which has Xilinx's Virtex-II.
- Virtex-II (XC2V6000-4)
- 18Mb SRAM x 8 (Synchronous SDR)
- 256Mb SDRAM x 2
ReCSiP-2 Board
ReCSiP Board is our second 64bit/66MHz PCI card, which has Xilinx's Virtex-II Pro. First version of ReCSiP-2 board was out in 2004, with Micron's QDR-I SRAMs. Now we're designing the second version of ReCSiP-2 board, with GSI's SigmaQuad-II (QDR-II compatible) SRAMs.
- Virtex-II Pro (XC2VP70, -5 or -6)
- 18Mb SRAM x 8 (QDR-I or QDR-II)
- DDR-SDRAM SO-DIMM Socket
- FDK's hardware random number generator
Drivers and Interface Logic
The development of memory and host interfaces is also going on (but, very slowly...). Because current implementation of ReCSiP has no host interface for "logging" of the results, however, this will done in Q2 of 2005.
- Interface Logic
- Slave Access
- Master Access (now debugging!!)
- QDR-I/II SRAM interface
- DDR-SDRAM interface (now debugging!!!)
- Drivers
- Linux
- FreeBSD
- MacOS X
TODO
- Full SBML/SBW integration
- Fully-automated generation mechanism of simulation hardwares (including the switch, integration modules and host interface)
- Hardware-software interface for "logging" the time-series result of simulations
- Master DMA transfer mechanism by the ReCSiP-2 board and its driver